The present invention relates to a method of storing information in a computer memory, specifically Flash memory. Flash memory consists of large arrays of cells that represent digital information. Typically, each cell represents one bit of data. Some types of Flash cells using Multi-Level Cell (MLC) technology are able to represent more than one bit in a single cell.
In the physical world, each cell carries in fact a voltage level derived from a continuous spectrum, the spectrum called the xe2x80x9cvoltage windowxe2x80x9d. The voltage levels are divided into non-overlapping bands, each representing a digital value. In single-bit-per-cell Flash there are two such bands, one representing the xe2x80x9c0xe2x80x9d bit value, the other the xe2x80x9c1xe2x80x9d bit value. In MLC Flash with m bits per cell, there are 2mnon-overlapping bands, one for each possible value of the m bits. This existing Flash technology is referred to hereinafter as xe2x80x9cnominal m-bit-per-cell Flash technologyxe2x80x9d.
Increasing the information content of Flash cells is a central goal of Flash memory design. Such an increase will result in lower cost per Megabyte of memory and increased bit density, resulting in smaller area, smaller power dissipation and higher production yields.
Much effort has been invested in MLC technology, and 2 bits-per-cell Flash devices are now available commercially. The limiting factor is the number of non-overlapping voltage bands that can be placed in the voltage window, where 2 bits per cell need 4 bands, and 3 bits per cell need 8 bands. The voltage window cannot be increased in size beyond some limit, while each of the voltage bands has a finite width that is dictated by several facts of Flash technology:
The precision of the read and program circuits of the cell voltage level is finite and limited by random noise that is inherent in all such circuitry.
The number of program/erase cycles in Flash is limited, due to effects of wear. These effects include the shrinkage of the voltage window, and the introduction of a bias in each of the voltage bands. Consequently, the MLC capability of Flash is reduced with wear.
Flash cells lose their programmed voltage slowly when not programmed for a long time. Therefore, to avoid misreading a cell with an incorrect value, the voltage bands must be far apart enough to avoid a cell voltage drifting into the wrong band. This effect places a time limit on the data retention of Flash cells.
To achieve higher MLC capability, researchers have sought ways to control these noise and bias effects. Harari et al. in U.S. Pat. No. 5,163,041 introduced the device of reference cells, where extra Flash cells are attached to a group of Flash cells, and programmed with the voltage level of each bit representation. Cell values are read in comparison with the level of reference cells, rather than in comparison with any fixed value. Since the reference cells undergo the same programming history as the data cells they are attached to, they serve to cancel most of the systematic bias caused by wear and voltage loss, but cannot solve the inherent signal-to-noise reduction caused by these effects.
It should be noted that a voltage band does not have a clear-cut edge. In fact, there is a statistical distribution of likely voltages around its center, and the width of the band is a statistical measure of that distribution. The bands are non-overlapping only up to a certain probability, and they in fact overlap to a small degree that may produce a bit read failure (BRF). The voltage bands are designed with some constrains, i.e. to produce a nominal bit read failure rate (BRFR) smaller than some target (for example 10xe2x88x9213), given a target of some program/erase cycling endurance (for example 100,000), and some minimal data retention period (for example 10 years). As used hereinafter, xe2x80x9cnominal BRFxe2x80x9d and/or xe2x80x9cnominal BRFRxe2x80x9d refer to existing Flash, and more generally, to existing solid state memory BRF or BRFR characteristics. These given constraints set the limit for the MLC capability of the Flash technology. While greater multi-bit capability could be achieved by relaxing these target specifications (i.e. relaxing the nominal BRFR), such relaxation does not truly increase the information content of the Flash cells.
There is thus a widely recognized need for, and it would be highly advantageous to have, a method by which the information content can be truly increased in both single-bit-per-cell and multi-level cell Flash technology. This increase in information content would result in reduced cost per megabyte of memory, or, alternatively, for a given memory size, in lower dissipative power loss and lower manufacturing cost, among other advantages.
The present invention presents a method by which the information content can be truly increased in both single-bit-per-cell and multi-level cell Flash technology, as well as in other memories.
According to the present invention there is provided a method for storing and retrieving a binary number including b data bits, comprising the steps of: a) providing a memory including a number n, greater than 1, of cells, each cell having a respective adjustable parameter; and b) setting the parameters to collectively represent the number.
According to a preferred embodiment of the method of the present invention, the method further comprises the steps of: c) measuring the parameters; and d) decoding the measured parameters collectively to recover the number.
According to the present invention there is provided a method for storing and retrieving a binary number including b data bits in a nominal m-bit per cell memory technology having a nominal bit read failure rate, m being at least 1, the method comprising the steps of: a) providing a plurality n less than b/m of cells; b) assigning each cell at least 2m+1 adjustable parameter values; and c) setting the parameter values to collectively represent the number, whereby the nominal bit read failure rate is preserved.
According to a preferred embodiment of the method of the present invention, the method further comprises the steps of: d) measuring the parameter values; and e) collectively decoding the measured parameter values to recover the number.
According to the present invention there is provided a storage device for storing a binary number of b bits, the device comprising: a) a memory having a plurality n of nominal m-bit-per cell cells, n being smaller than b/m; b) a plurality of adjustable parameters used to represent the bits; c) storing means to collectively set the adjustable parameters to store the number in the memory; and d) retrieving means to collectively measure the parameters to retrieve the number from the memory.